Introduction
The increasing global demand for energy-efficient and sustainable systems has driven significant advancements in power electronics, particularly in DC-DC conversion technologies1. Traditional Boost converters, while effective in many applications, often have difficulty to achieve the high-voltage gains required in modern power systems, such as photovoltaic solar systems2, electrical vehicles (EV)3, High-Voltage Direct Current (HVDC) power transmission systems4, water pumping systems5, or others. Addressing the limitations of conventional topologies, this work introduces a novel interleaved quadratic DC-DC Boost converter designed to provide significantly higher voltage gain without sacrificing efficiency.
Over the years, numerous DC-DC Boost converter topologies have been developed for different applications in a wide range of emergent multidisciplinary engineering fields, such as renewable energy sources (RES), photovoltaic solar energy conversion, EV, energy storage systems (ESS), fuel cells, among others.
Typically, DC-DC converters can be classified according to different features, such as isolated 6,7 or non-isolated8,9, unidirectional10,11 or bidirectional12,13, voltage-fed14,15 or current-fed16,17, hard-switch18,19 or soft-switch20,21, minimum-phase22 or non-minimum-phase23. Most of these DC-DC converters are well represented in 24–27. Another way to classify the DC-DC converters is specifying their voltage Boost technique. Some of the most well-known techniques are the switched capacitors28,29, voltage multiplier cells30,31, switched inductors32,33, voltage lift34,35 and multi-stage/-level36,37 topologies. A review of some of these step-up voltage techniques can be found in 38–40. Nowadays, engineering research is also focused on the development of converters with higher reliability, higher efficiency, combined with less volume, weight and cost41.
Among the DC-DC converter topologies developed recently that have stood out for the high-voltage gains obtained are those that present quadratic gains. In this way, is possible to highlight some significantly important topologies developed with such features. The solution proposed in 42 is a transformerless high step-up DC-DC converter with a quadratic voltage gain. In this converter, using a duty cycle greater than 0.309 is possible to achieve a higher voltage gain than the classic Boost converter. This solution includes three switches, five diodes, two inductors and three output capacitors. Despite its interest, this solution requires too many components when compared with other solutions. Other quadratic gain topology can be found in 43, where the authors propose a modified classic DC-DC buck-boost converter. Since this topology allows a buck-boost operation, it is only necessary to control one power switch for each operation mode and the additional power switches remain always ON or always OFF. By controlling only one power switch, they developed a setup capable of achieving a quadruple voltage gain for a duty cycle of 0.5. Another similar topology can be found in 44, which created a quadratic high-gain Boost converter, where it was possible to obtain a gain of two times the input voltage at the output with a duty cycle of 0.50. More recently a new DC-DC Boost converter setup with quadratic gain was proposed45. In this solution using a duty cycle of 0.50 is also possible to achieve a triple output voltage. This solution includes one switch, three diodes, two inductors and two output capacitors. Recently, a new quadratic DC-DC Boost converter topology was proposed in 46, which can achieve a quintuple output voltage with a duty cycle of 0.50. This solution requires only one switch, four diodes, two inductors and three capacitors. The main disadvantage of this solution is that the switch must withstand the maximum output voltage.
It is well-known that high-voltage gain is critical in applications with low input voltages, such as those using a reduced number of solar panel strings or where, due to weather variability sometimes produce reduced voltages, and it required to efficiently convert them into much higher output voltages47. Most quadratic DC-DC Boost converters typically offer voltage gains of three to four times the input voltage, which may not be sufficient for advanced applications. The interleaved quadratic Boost topology proposed in this study aims to overcome these limitations by achieving an extended voltage gains over eight times the input voltage, or six times considering a duty cycle of 0.50, providing a more effective solution to integrate additional RES systems. This converter is also characterized by a simple control technique, continuous input and output current, reduced switching voltage stress over the power devices. The proposed solution takes advantage of the interleaved operation, which allows to use multiple circuits (or phases) to process power in parallel. These circuits are operated with time-shifted (interleaved) switching signals to achieve improved performance compared to a single-phase or single-circuit converter. Also, the interleaved operation avoids the need of large output capacitors. The solution is also able to achieve good efficiency according to some preliminary experimental results.
This paper presents the theoretical framework behind the proposed interleaved quadratic DC-DC Boost topology, complemented by some experimental results to confirm the theoretical results and efficiency. This paper is organized into five main sections. Section I is dedicated to the introduction of this subject and importance of DC-DC converters in most modern applications, followed by a brief state-of-the-art over DC-DC converters with quadratic gain. Section II provides a detailed explanation of all the design procedures and considerations on the prototype of the proposed converter. Section III presents a comparison between the proposed converter and other interleaved quadratic Boost DC-DC converters already proposed and implemented in the literature. Section IV is dedicated to presenting and demonstrating the laboratory setup and validation of the results regarding the operation principle, voltage gain obtained and efficiency. Finally, section V presents some conclusions.
Methods
Our investigation methodology was based on an initial theoretical approach using mathematical equations to describe the operation of the electrical circuit and evaluate the performance compared to other topologies, followed by the validation through some computational simulations using MATLAB/SIMULINK software. Next, the operation of the proposed converter was also confirmed by several experimental tests using a laboratory prototype developed exclusively for these tests. The next subsections are dedicated to show these procedures.
Power Circuit Layout of the proposed quadratic Boost DC-DC converter
Figure 1 shows the diagram of the interleaved quadratic Boost DC-DC converter proposed in this paper. It is a new topology that has never been published before, according to extensive research conducted in the main bibliographic reference resources in the field. The power circuit consists of an input inductor, Lin, along with two input diodes, Din1 and Din2, and a capacitor, Cin. Connected to these components are two additional circuits, one at the top and another at the bottom, each consisting of and inductor, L1 and L2, a capacitor, C1 and C2, and a diode, D1 and D2, respectively. Finally, to ensure the capability of voltage regulation and Boost operation, two power MOSFET, S1 and S2, are included, controlled by a command circuit through their gates, represented in the figure as G1 and G2, respectively.
Figure 1. Circuit topology of the proposed interleaved quadratic DC-DC Boost Converter.
Operation mode analysis in steady-state
The converter under study has four different operation modes, all in continuous conduction mode (CCM), depending on the operation of the two switches, S1 and S2. Although both power semiconductors can operate simultaneously (overlapping the conduction mode) for duty cycles above 0.50, this mode of operation is not advantageous for lower duty cycles, as it generates higher current peaks without resulting in improved voltage gain. Therefore, in the following analysis, it will be considered whether the converter operates with S1 turned ON and S2 turned OFF or S1 turned OFF and S2 turned ON or both switches turned OFF, providing four different operating intervals as explained next. Figure 2 shows a simplified representation of a classic PWM (Pulse-Width-Modulation) control strategy in order to achieve the described operation mode. This is considered an interleaved operation.
Figure 2. PWM switching strategy of S1 and S2.
In the following figures, the four stationary operation modes are illustrated in detail, where the current flow directions in the different paths are represented with different colours to help understanding the operation principle of the converter.
S1 turned ON and S2 turned OFF (δ1Ts). During this operating mode, the input diode Din2 is turned OFF, while the input diode Din1 is turned on. Also, during this mode, the input inductor Lin, discharges the energy accumulated in the previous operating mode over the input capacitor Cin which is in charging mode. Meanwhile, the diode D1 is also turned OFF because the inductor L1 is charging and the capacitor C1 is discharging, creating a reverse voltage over D1. On the other hand, D2 is turned ON, meaning that L2 is discharging the energy previously accumulated, and as a result, C2 is in charging mode. The current flow described is illustrated in Figure 3.
Figure 3. Current flow analysis when S1 turned ON and S2 turned OFF (δ1Ts).
S1 OFF and S2 OFF (δ2Ts). In this operating mode, Din2 remains turned off while Din1 remains turned ON. Similar to the previous operating mode, Lin is still discharging and Cin in charging mode. Both D1 and D2 are now turned ON since both inductors, L1 and L2, are discharging the accumulated energy over C1 and C2, respectively. The current paths described can be found in Figure 4.
Figure 4. Current flow analysis when S1 and S2 are turned OFF (δ2Ts).
S1 OFF and S2 ON (δ3Ts). In this operating mode, after turning ON the switch S2, Din2 turns ON to flow the current over the input inductor Lin, while Din1 turns OFF due to reverse voltage. Thus, Lin is charging, and Cin is discharging the accumulated energy in the previous operating mode over the inductor L2, which is storing energy. As a consequence of passive components polarity, D2 becomes reverse-biased and turned off, while C2 starts to discharge over the load. In the opposite direction, D1 is forced to turn ON to discharging the energy accumulated over the inductor L1 into C1, which is in charging mode. Figure 5 shows the representation of the current path flow described now.
Figure 5. Current flow analysis when S1 is turned OFF and S2 is turned ON (δ3Ts).
S1 OFF and S2 OFF (δ4Ts). In this operating mode, both switches are turned off and the current’s path flow is the same as the ones presented in the interval δ2Ts.
Following the operation modes described previously, it can be observed and concluded that the current in the inductor L1 increases when the switch S1 is turned ON and decreases when S1 is turned OFF. This means that the switching state of S1 does not affect the current in Lin and L2. On the contrary, the current in the inductors Lin and L2 increase when switch S2 is turned ON and decreases when S2 is turned OFF. This means that the switching state of S2 does not affect the current in L1. This indicates a partially independent operation of the two power switches, when the switching states of S1 and S2 do not overlap. According to the principle of operation detailed in the previous subsection, it is possible to obtain the theoretical waveforms of the four-operating mode of the proposed converter (see Figure 6). When analysing the evolution of the voltage across each inductor and semiconductor presented in this figure is possible to establish the voltage relationships shown in Table 1.
Figure 6. Theoretical wave forms of the proposed DC-DC Converter.
Table 1. Voltage relationship between components.
| Voltage/Time | (δ1Ts) | (δ3Ts) | (δ2 Ts, δ4Ts) |
|---|
| vL1 | -vCin | vC1 | vC1 |
| vL2 | vC2 | -vCin | vC2 |
| vLin | vin - vCin | vin | vin - vCin |
| vDin1 | 0 | vCin | 0 |
| vDin2 | vC2 | 0 | vC2 |
| vD1 | vCin + vC1 | 0 | 0 |
| vD2 | 0 | vCin + vC2 | 0 |
| vS1 | 0 | vCin + vC1 | vCin + vC1 |
| vS2 | vCin + vC2 | 0 | vCin + vC2 |
According to Table 1, as result of the analysis of the voltage relationships between components is possible to see that the maximum voltage stress over power devices S1 and S2 are vCin + vC1 and vCin + vC2, respectively, which is far reduced when compared to most DC-DC converters whose power devices must support the maximum output voltage.
In this way, it is possible to establish the following voltage relationships for each inductor. Assuming ideal components and considering one switching cycle, the relationship between the output and input current, function of the duty cycle, can be obtained through the volt-second relationship of the inductors L1, L2 and Lin, as presented from (1) to (3), respectively:
Knowing that (δ2 + δ3 + δ4) = (1 – δ1) and (δ1 + δ3 + δ4) = (1 – δ3), as well as δ1 = δ3 = δ; equalizing and solving the Equation (1) to Equation (3) to each capacitor voltage, it is possible to establish the voltage equations listed below from (4) to (6):
Equalizing and solving Equation (4) to Equation (6) in order to Vin, and knowing that Vout = vCin + vC1 + vC2, it is possible to establish the expression that characterizes the voltage gain of the proposed interleaved quadratic DC-DC converter (7):
Design considerations
In this section, the entire design process of the passive components used in the proposed experimental prototype will be presented and discussed. The following characteristics were considered in the design of the prototype: vin = 50 V, δmax = 0.5, RLoad = 450 Ω, Pout(max) = 200 W, vout (δmax) = 300 V, iout (δmax) = 300/450 = 0.67 A, ΔiLmax = 0.5 A, ΔvCmax = 1 V to 3 V, fPWM = 50 kHz, efficiency of 95%.
Inductors design
For the inductors design, the generic adopted expression to define the minimum inductance value is presented in (8). This expression is based on the linear variation of the current in the inductor and is well explained in most design chapters about DC-DC converters, such as 48–50.
Where vLmax is the maximum voltage applied to the inductor, δ is the maximum duty cycle intended for the converter, fPWM
is the switching frequency of the converter, and ΔiL is the maximum current variation (ripple) desired in the inductor. For the input inductor, Lin, the following equation can be used:
For the remaining inductors, L1 and L2, the following equation can be used:
Ferromagnetic material saturation analysis
The material of the inductors, applied in this prototype, uses a Litz 420x0.08 SE F155 G1 wire type (widely used in high frequency applications, as it reduces losses and the skin effect), a plastic inductor winding support from the CF model -E70-1S and a set of ferrite cores from model E70/33/32DG in “U” shape, from the manufacturer TDK, with type N87 ferrite. Using the manufacturer datasheet, it is possible to obtain some essential parameters (see Table 2) for analyzing the electromagnetic saturation of the ferrite core.
Table 2. Magnetic Parameters of the Ferrite Core E70/33/32DG.
| Magnetic Parameter | Value |
|---|
| Effective magnetic cross section (Ae) | 683 mm2 |
| Inductance factor (AL) | 250 nH |
| Effective magnetic length (le) | 149 mm |
| Saturation flow density (B) | 390 mT |
Thus, to calculate the maximum current value that can cross each inductor, before saturating the ferromagnetic material is possible to estimate the number of turns of each winding, taking into account the desired inductance value, L, (H) and the inductance factor, AL, (H) of the material adopted48–51.
After applying Equation (11) to each inductor, the values expressed below were obtained from (12) and (13).
Then, the permeability of the ferrite adopted, μ, (H/m) can be calculated from Equation (14).
Finally, using Equation (15) is possible to calculate the maximum current over each inductor prior to saturate the ferrite magnetic material.
Applying (15) for all the inductors, the current values can be calculated.
Capacitors design
Similarly, for the capacitors design, the generic adopted expression to define the minimum capacitance value is presented in (18). This expression is based on the linear variation of the voltage in the capacitors.
Where iCmax is, generally, the maximum current flowing through the capacitor, δ is the maximum duty cycle intended for the converter, fPWM is the switching frequency of the converter, and ΔvC is the maximum voltage variation (ripple) desired in the capacitor. For the input capacitor is necessary to obtain the input current, which can be obtained based on the output power, efficiency and input voltage (19). It was selected a maximum ripple ΔvCmax = 3 V for the input capacitor and ΔvCmax = 1 V for the remaining capacitors.
For the capacitors C1 and C2, the following Equation (20) can be used.
This calculation shows that the proposed interleaved converter requires small capacitor which is an advantage over other topologies.
Comparison with other interleaved quadratic DC-DC Boost topologies
This section is intended to compare the proposed solution with other interleaved quadratic Boost DC-DC topologies presented in the references52–55. Table 3 shows a comparison about the number of components needed to achieve the voltage gain obtained by each converter and maximum voltage stress over the power devices.
Table 3. Comparison between some different interleaved quadratic Boost DC-DC topologies.
| Topologies |
|---|
| Proposed | 52 | 53 | 54 | 55 | 56 |
|---|
| Number of Switches | 2 | 1 | 2 | 2 | 2 | 4 |
| Number of Diodes | 4 | 3 | 6 | 4 | 6 | 2 |
| Number of Inductors | 3 | 2 | 4 | 4 | 4 | 4 |
| Number of Capacitors | 3 | 2 | 4 | 3 | 3 | 2 |
| Voltage gain* | | | | | | |
| Maximum Voltage stress over switches | | Vout | | | Vout | |
The comparison between these topologies shows that the solution proposed in this paper is not the one that achieves the highest voltage gain, but presents a relative high voltage gain with less components and is one that presents the most reduced voltage stress over the power devices.
Figure 7 compares the theoretical voltage gain characteristics of each DC-DC Boost converter topology. As shown in Figure 7, the proposed converter is able to provide a voltage gain output of six times the input voltage for δ = 0.5. The solution presented in 56 presents the best voltage gain bellow 0.45 but the voltage gain rate above 0.45 is smaller than the proposed topology.
Figure 7. Comparison between the proposed interlevead quadratic DC-DC converter other similar topologies regarding the voltage gain versus the duty cycle.
Laboratory validation
The practical tests of the proposed converter prototype were carried out considering a maximum output power of 200 W, using a constant load resistance of 450 Ω, an input voltage of 50 V and a switching frequency of 50 kHz. The inductors are L1=L2=2mH and Lin=1mH. The capacitors are Cin=22μF and C1=C2=10μF (normalized values). It should be noted that all practical results were always compared with a computational validation of the converter circuit operation, employing the MATLAB®/SIMULINK® software. Figure 8 shows a wide-angle photograph of the workbench with the proposed converter prototype and all the essential devices to test the solution.
Figure 8. Workbench with the proposed DC-DC converter prototype (1–Laptop with the circuit simulation in MATLAB®/SIMULINK®; 2 – Load resistor; 3 – Inductor; 4 – Printed Circuit Board (PCB) of the power circuit and gate drive circuit; 5 – Power supply for the control circuit; 6 – Power Supply for the power circuit; 7 – Signal generator; 8 – Oscilloscope; 9 – Breadboard with the PWM control circuit).
Inductors and power devices waveforms
Figure 9 shows the experimental result of the three inductor currents obtained from the power circuit of the proposed converter for δ = 0.4 and relation with the switching of the power devices. The results presented in Figure 9 confirm the dependence between each inductor and one of the power switches, specifically, the state of charge of Lin and L2 depends on the conduction state of S2, and the same situation occurs between L1 and S1. The mean current values are: iLin = 1.169 A, iL1 = 810.2 mA and iL2 = 758.2 mA.
Figure 9.
Inductor currents and power devices voltages for δ = 0.4: a) iLin and vS2; b) iL1 and vS1; c) iL2 and vS2.
Diodes and power devices waveforms
Figure 10 illustrates the experimental results of the relationship between the diodes and the power switches voltage for δ = 0.4. According to the results shown above (Figure 10a) and Figure 10b)), the conduction states of D1 and D2 are symmetric to the conduction state of S1 and S2, respectively. On the other hand, the conduction states of both input diodes Din1 and Din2 are dependent on the S2 (see Figure 10c)) state, just like iLin, as concluded before in Figure 8a). Notice that the power devices voltage waveforms are different depending on the experimental result for the same duty cycle, which is probably due to coupling of common mode noise, which is more intensive as the switching frequency increases.
Figure 10.
Diodes and power switches voltages for δ = 0.4: a) vD1 and vS1; b) vD2 and vS2; c) iLin , vDin1 and vDin2.
Capacitors and power devices waveforms
Figure 11 shows the experimental results of each capacitor and the power switches voltages for δ = 0.4. Interpretating the results shown in Figure 11, and remembering the symmetric relation between D1 and S1, along with D2 and S2, it is clear the correspondence between the state of charge of both Cin and C2 and S2, as well as, between C1 and S1. Making a parallel analysis between the results of Figure 9 and Figure 11, it is also possible to observe when an inductor is discharging the corresponding capacitor is charging and vice-versa. The mean voltage values are: vCin = 80.26 V, vC1 = 52.20 V and vC2 = 50.20 V. Notice that in the following figure, the Ch2 voltage gain is only 2V/div, and the reference is virtually several divisions bellow the minimum visible at the screen (this Peaktech oscilloscope allows this configuration). Thus, the noise is not so high as it seems at first sight.
Figure 11.
Capacitor and power switches voltages for δ = 0.4: a) vCin and vS2; b) vC1 and vD1; c) vC2 and vD2.
Output voltage and voltage gain
In this subsection several experimental results are presented of the output voltage, output current and a voltage gain comparison for different duty cycles. Figure 12 features the experimental voltage and current output result obtained with δ = 0.4. Observing Figure 12 it is possible to see that for δ = 0.4 the proposed prototype is able to produce an output voltage vout = 189.8 V, which translates to a voltage gain (vout/vin) of 3.66. The mean value of the output current is equal to 453.4 mA.
Figure 12. Output voltage and current for a duty cycle, δ = 0.4.
Figure 13 shows the experimental result of the output voltage and output current obtained in the prototype for δ = 0.5. Observing Figure 13 with this duty cycle is possible to observe an output voltage vout = 291.00 V, which translates to a voltage gain (vout/vin) of 5.82. The mean value of the output current is equal to 690.6 mA.
Figure 13. Output voltage and current for a duty cycle, δ = 0.5.
As a final experimental result, the prototype was tested with a duty cycle value δ = 0.6. Figure 14 shows the output voltage in this condition. According to Figure 14, the experimental result obtained of the output voltage obtained with a duty cycle δ = 0.6 is 436.7 V. Which means it is possible to get a voltage gain (vout/vin) of 8.62. Above this duty cycle is difficult to increase the voltage gain due to increased losses.
Figure 14. Output voltage for a duty cycle, δ = 0.6.
Results
This section discusses the results obtained based on the experimental test observations, oscilloscope waveforms, and measured voltages and currents. Figure 15 compares the theoretical voltage gain of the proposed converter, the computational simulation results (simulated in MATLAB®/SIMULINK® using the average power losses available in the Simscape Power Systems toolbox) and also the experimental voltage gain obtained.
Figure 15. Comparison between theoretical, simulation and experimental voltage gain.
Analyzing Figure 15 is possible to observe in the duty cycle range from 0.05 to 0.60, the output voltage and voltage gain of the experimental prototype shows a high degree of similarity when compared with the simulation and theoretical calculations. Additionally, it is confirmed that with a duty cycle of 0.20, a gain voltage greater than 1.7 is achieved, with a duty cycle of 0.30, a voltage gains greater than 2.5, with a duty cycle of 0.40, a voltage gains greater than 3.6 and with a duty cycle of 0.50, a gain greater than 5.8 is achieved. A maximum gain of 8.62 was achieved with a duty cycle of 0.60. Behind this duty-cycle is difficult to improve the voltage gain since the losses become extremely high.
Figure 16 shows the graphical result of the efficiency obtained in both simulation and experimental tests, as function of the converter duty cycle.
Figure 16. Comparison between the simulation and the experimental results concerning the converter efficiency.
After analysing the results presented in Figure 16, a close correlation is observed between the efficiency variation and the duty cycle applied to the converter. For a duty cycle variation from 0.05 to 0.60, an efficiency range around 97% to 90% was obtained in the simulation tests and an efficiency range around 96% to 90% was obtained in the experimental tests. It is also observed that a maximum efficiency of 96.79% was achieved for a duty cycle δ = 0.25.
Figure 17 illustrates the evolution of the experimental efficiency and voltage gain over the duty cycle. The purpose of this relationship is to evaluate at which output voltage gain value it is possible to achieve the best efficiency, helping us to identify an optimal operating point for the proposed DC-DC converter prototype.
Figure 17. Comparison between experimental voltage gain result and experimental efficiency result.
A maximum efficiency of 96.79% was achieved for a duty cycle around δ = 0.25.
Examining Figure 17 is possible to observe that the optimal operating point of the converter happens with a duty cycle of δ =0.25 which results in a voltage gain of 2.09 (marked in red in the figure). However, it is clear that, up to a duty cycle of 0.60, the converter maintains an efficiency between 90% and 96%, which can be considered quite satisfactory. At the maximum value for which it was designed, with a duty cycle of 0.50, the converter presents a voltage gain of 5.82 and an efficiency of 94.76%. Additionally, there is very little variation in efficiency, as it remains between 96% and 95% until reaching a duty cycle of 0.50.
Finally, Figure 18 shows the relation between the output power and the output voltage gain of the proposed topology considering a fixed duty cycle of 0.50, showing certain limitations over the output gain due to the several losses.
Figure 18. Output voltage gain versus Output Power, considering a fixed duty cycle of 0.50.
Discussion
DC-DC converters play an important role in the integration of different Renewable Energy Sources (RES) into DC distribution networks or as front end devices to connect to DC-AC converters, according to the desired requirements and adopted equipment interface. There is a constant research regarding the design of new DC-DC converter topologies with high-voltage gain ratio and boost ability to extend the operation of RES, and other sources, all over the available voltage ranges, extracting efficiently as much energy as possible. In this paper it was made a brief research about other type of DC-DC converters and it was decided to create a new topology interleaved quadratic DC-DC converter. Quadratic DC-DC converter are some of the topologies that can achieve high voltage gains and are the most suitable for several RES applications due to the variability of most of them, which are dependent on weather conditions, location, distribution system and other aspects. When compared with other topologies in the literature, especially other quadratic DC-DC converters, the proposed topology is the one with higher voltage gain, but present a reduced number of components and the interleaved solution allows to reduce the voltage and current stress over power devices which allows to increase the reliability of the solution. The laboratory prototype was tested in several conditions during several days to evaluate the overall performance, namely the voltage and current stress, robustness, overheating issues, hot spots, electromagnetic noise, efficiency, sensitivity to parameters variation and other aspects. Regarding the electromagnetic noise, some adjustment need to done as future work in the printed circuit board and components, but the overall performance is quite acceptable. This will allow to improve some waveform and interference due to electromagnetic noise. The efficiency was measured in several conditions and real values between 90% (worst conditions) and 96% (best condition) were achieved. Other relevant aspect is the reduced value of capacitors, due to the interleaved operation. This leads to reduced stress over capacitors and distributed voltage. Notice that the output voltage is the sum of the voltage over the three capacitors. A low power laboratory prototype was developed but is possible develop a similar high power converter.
Conclusions
This paper proposed a new interleaved quadratic DC-DC boost converter topology with high-voltage gain, confirming the theoretical operation principle based on some experimental setup. The experimental results demonstrate that the proposed topology allows higher voltage gains than most well-known quadratic topologies, reaching a voltage gain from six to eight in a real prototype without degrading the efficiency significantly. The proposed converter provides continuous input and output current and a simple PWM control strategy. Furthermore, it was possible to optimize the converter's efficiency by adjusting the duty cycle, which plays a crucial role in minimizing conduction and switching losses. The obtained results indicate that there is an optimal operating point where efficiency is maximized, achieving an efficient balance between voltage gain and associated losses. Additionally, there is a very small variation in efficiency, which remains between 95% and 96% up to a duty cycle of 0.50, where a voltage gain of 5.82 is achieved in a real setup. However, when the voltage gains increase behind this point, the efficiency began to decrease, resulting in an evident trade-off between maximizing voltage gain and energy efficiency. This trade-off is particularly relevant in solar photovoltaic applications, where it is necessary to find an appropriate compromise between voltage gain and efficiency based on the specific requirements of the system.
Ethics and consent
Ethical approval and consent were not required.
